1. Field of the Invention
The present invention relates to a control system for a plurality of input/output apparatuses (I/O apparatuses) in an electronic computer system, and more particularly to a control system for an I/O apparatus which is capable of dealing with the problem of an erroneous transfer of data between the main memory and the I/O apparatus controlling device.
2. Description of the Prior Art
Control systems for a plurality of I/O apparatuses in accordance with the prior art are illustrated in FIGS. 1 and 2 attached to the present specification. In FIG. 1, an electronic computer system comprising a central control unit 2, a main memory 1, a channel control device 3, I/O apparatus controlling devices 51, 52, . . . , 5n, and, I/O apparatuses 61, 62, . . . , 6n. I/O apparatus controlling devices 51, 52, . . . , 5n are connected to a common bus 4 to the channel control device 3. Each of the I/O apparatus controlling devices 51, 52, . . . , 5n includes a bus supervising circuit 51A, 52A, . . . , 5nA. The main memory 1 permits access from either the central control unit 2 or the channel control device 3. The channel control device 3 exchanges information with the I/O apparatus controlling devices 51, 52, . . . , 5n by way of the common bus interface control through the common bus 4, and accordingly controls the corresponding I/O apparatuses 61, 62, . . . , and 6n. The I/O apparatuses 61, 62, . . . , 6n effect the data transmission with the central control unit 1 through the I/O apparatus controlling devices 51, 52, . . . , 5n and the channel control device 3 in accordance with the start sequence instruction from the central control unit 2.
The operation of the system shown in FIG. 1 is illustrated by the information flow chart of FIG. 2. At first, at the stage of the Execution of Instruction signal (a), the central control unit 2 sends an Instruction of Start signal (b) and an I/O Address Information signal (c) which indicates the selected I/O apparatus which is to be controlled, to the channel control device 3. In accordance with the Instruction of Start signal (b) and the I/O Address Information signal (c), the channel control device 3 sends a Request for Control Information signal (d) to the main memory 1, and accordingly a Control Information signal (e) is sent to the channel control device 3. In accordance with the I/O Address Information signal (c), the Control Information signal (e) is sent to the corresponding I/O apparatus controlling device 51, 52, . . . or 5n so that the I/O apparatus corresponding to the I/O apparatus controlling device is actuated.
Assume that the Control Information signal (e) is an instruction to transfer data from one of the I/O apparatuses 61, 62 . . . 6n to the main memory 1. In accordance with the Control Information signal (e), a Request for Transfer signal (g), (g') and Data signal (h), (h') are sent from one of the the I/O apparatus controlling devices 51, 52, . . . , 5n to the main memory 1. If the Data signal (h), (h') is correctly received by the main memory 1, a Main Memory Response signal (i) is sent from the main memory 1 to the channel control device 3, and accordingly a Response signal (j) is sent from the channel control device 3 to one of the I/O apparatus controlling devices 51, 52 . . . 5n. After that the control proceeds to the next step.
On the other hand, if some errors, such as an incorrect receipt of the Data signal (h), (h') in the main memory 1 or a detection of erroneous data transfer by the channel control device 3, occur in the data transfer between the I/O apparatuses 61, 62 . . . 6n and the main memory 1, the following process will take place. That is, the channel coontrol device 3 sends a Reset signal (s), instead of a Response signal (j), to the I/O apparatus controlling devices 51, 52 . . . 5n, in accordance with either a Main Memory Response signal (i) indicating the error from the main memory 1 or an error detection signal by the channel control device 3 itself. Thus, all of the operating I/O apparatuses 61, 62 . . . 6n connected to the I/O apparatus controlling devices 51, 52 . . . 5n are caused to be reset and stopped. Simultaneously with the stopping of the I/O apparatus controlling devices 51, 52 . . . 5n, the channel control device 3 notifies the central control unit 2 of the occurrence of the error by sending a Request for Interruption signal (p). A Request for Memory Access signal (g) is sent from the channel control device 3 to the main memory 1 so that an Error Information signal (r) is written into a specific address in the main memory 1. The above mentioned Request for Transfer signal (g), (g') includes only the address of the main memory 1 and the data which is to be stored in the main memory 1 or to be read out from the main memory 1 and does not include the address of any of the I/O apparatuses 61, 62 . . . 6n. It is not necessary to know the address of the I/O apparatus 61, 62 . . . 6n, because the channel control device 3 and the I/O apparatus controlling device 51, 52 . . . 5n corresponding to the I/O apparatus 61, 62 . . . 6n which is effecting the transfer is specifically connected through the common bus 4. Accordingly, the above mentioned Error Information signal (r) is only an information signal detected in the channel control device 3 and does not include the address of the I/O apparatus 61, 62 . . . 6n related to the error. Then, the central control unit 2 reads out the information stored in the specific address in the main memory 1 in accordance with the Error Information signal (r) and effects the predetermined error disposing process.
In the control systems for I/O apparatuses 61, 62, . . . 6n in accordance with the prior art as described above, although it is possible to confirm the type of errors which have occurred by way of the error information signal detected by the channel control device 3, the interruption from the side of the I/O apparatus 61, 62 . . . 6n does not take place except in the case where the transfer operation at the I/O apparatus 61, 62 . . . 6n side is informed when the information transfer from the main memory 1 to the I/O apparatus 61, 62 . . . 6n is normally completed and the case where the detection of an error is informed when the error is detected by the I/O apparatus controlling devices 51, 52 . . . 5n. It should be noted that the address information of the I/O apparatus 61, 62 . . . 6n is delivered to the common bus 4 when an interruption takes place with regard to the I/O apparatuses 61, 62 . . . 6n. Thus, the address of the I/O apparatus 61, 62 . . . 6n is communicated to the channel control device 3 due to the interruption in the common bus 4 by the I/O apparatus controlling devices 51, 52 . . . 5n. Accordingly, the address of the I/O apparatus 61, 62 . . . 6n in question is discovered. Therefore, in the common bus interface control system, the address of the I/O apparatus 61, 62 . . . 6n cannot be known to the channel control device 3 when an error occurs in the transfer between said I/O apparatus 61, 62 . . . 6n and the main memory 1, except for the above described two cases. As a result, the above mentioned Reset signal (s) resets all of the I/O apparatuses 61, 62, . . . , 6n under the common bus interface control between the channel control device 3 and the I/O apparatus controlling devices 51, 52 . . . 5n so that all of the I/O apparatuses 61, 62, . . . , 6n are brought back to their initial status and stopped. This operation is considered unfavorable, because even the I/O apparatuses 61, 62 . . . 6n which need not be stopped are caused to be stopped. In addition, since it is required that the central control unit 2 confirm the operation status of all I/O apparatuses 61, 62 . . . 6n by reading out the information registered in the registers for all I/O apparatuses 61, 62 . . . 6n connected to the channel control device 3 which delivers the error information signal and effects a re-start of the stopped operation or repetition of the whole process from the beginning, the amount of information to be disposed becomes very large. This increase of the amount of information is also considered unfavorable, because it places a heavy burden on the central control unit 2.
The present invention has been proposed in order to provide a solution to the above explained problems in the prior art system.
The above explained prior art system is disclosed in, for example, U.S. Pat. Nos. 3,710,324 and 3,815,099.